1. Technical Field
The present disclosure relates to a semiconductor device and more particularly, to a semiconductor chip and a multi-chip package having a plurality of stacked semiconductor chips.
2. Discussion of Related Art
Package technologies have been developed such as multi-chip packages and the system in package (SIP), in which, for example, memory, logic and analog devices are combined and packaged in a single chip, thereby reducing the number of components required to implement various functions and the size and cost of the semiconductor device.
In a conventional multi-chip package, a plurality of chips is mounted within a single package such that the chips are stacked on one another with buffer layers interposed therebetween, wherein the bonding pads on the chips are connected to pads on a lead frame or a PCB substrate by bonding wires. However, a long distance between the pads interconnected by the bonding wires may result in, for example, undesirable bending of the bonding wires due to an applied tensile force, unreliable wire bonds, or undesired contact of the wires onto non-designated portions of semiconductor chips. Conventional multi-chip packages may include an interface chip between semiconductor chips.
FIG. 1 is a view illustrating a conventional multi-chip package with an interface chip interposed between chips.
Referring to FIG. 1, a first semiconductor chip 20 is stacked on a substrate 10, and a second semiconductor chip 40 is stacked on the first semiconductor chip 20 with an interface chip 30 interposed therebetween. The interface chip 30 includes an interconnection layer 32 radially formed from a central portion to an edge portion. Pads 12 and 42 are formed on the substrate 10 and the second semiconductor chip 40, respectively. The pads on the substrate 10 are electrically connected to the pads on the second semiconductor chip 40. The interface chip 30 serves as an intermediate medium for establishing an electrical connection between the semiconductor second chip 40 and the substrate 40. The pads or the substrate 10 and the interconnection layer 32 of the interface chip 30 are electrically connected by bonding wires 14, and the interface chip 30 and the second semiconductor chip 40 are electrically connected by bonding wires 42, so that the substrate 10 and the semiconductor chip 40 are electrically connected through the interface chip 30. The stacked structure of the multi-chip package may prevent defects caused when a tensile force is applied to the bonding wire due to a difference in height and size between the semiconductor chip 40 and the substrate 10 and as a result of the long distance between the pads thereof.
Establishing electrical connections between semiconductor chips or between a substrate and a semiconductor chip using an interface board may increase stack size and can cause an excessive increase in the thickness of a package. The size of the interface board is greater than the size of the semiconductor chip, because pads on the semiconductor chip are connected to an interconnection layer of the interface board by bonding wires, and thus the stacking order can be limited depending upon the size of the semiconductor chip.